Field of the Invention
The invention relates in general to a low dropout regulator (LDO), and more particularly to a highly efficient LDO that uses a transistor having a low withstand voltage as a driving stage.
Description of the Related Art
Power lines having different voltages are frequently required in an integrated circuit. For example, a 3.3V power line AVDD3P3, a 1.0V core power line DVDD, a 1.5V input/output (I/O) power line AVDD1P5, and a 1.0V clock tree power line AVDDTREE may be designed in an integrated circuit. An integrated circuit may receive an external power supply from only one or two fixed voltages. For other power lines having different voltages in the integrated circuit, the power voltage of each of the power lines is stabilized through conversion performed by an internal power converter. A low dropout regulator (LDO) is a type of converter, and is extensively adopted in the field of integrated circuit design because of its simple structure. Despite having the same source voltage, instead of short circuiting each other, the core power line DVDD and the clock tree power line AVDDTREE are isolated from each other to prevent noise generated at one of the power lines from affecting operations of circuits powered by the other power line.
To operate under different source voltages, transistors having different withstand voltages may also be provided within an integrated circuit. The withstand voltage of a transistor represents a maximum value of a voltage across two ends of the transistor that the transistor can withstand. Given that the voltage across the two ends of the transistor does not exceed the withstand voltage, the transistor is entrusted with sufficient reliability. For example, an integrated circuit includes a core circuit. The core circuit is primarily used for logic operations, and includes core devices, e.g., a core NMOS transistor and a core PMOS transistor. To achieve a high operation speed and low power consumption, the core circuit is powered by the 1V core power line DVDD, and the core device has a withstand of only 1V. An integrated circuit may further include I/O devices, e.g., an I/O NMOS transistor and an I/O PMOS transistor. To have a higher capability of withstanding external high-voltage signals, an I/O device may need a withstand voltage that is as high as 1.5V, and may be powered by the 1.5V I/O power line AVDD1P5. In general, a device having a higher withstand voltage needs to achieve a certain current driving capability, and includes circuits that occupy a greater silicon area and have higher costs. In the application, the withstand voltages of the I/O device and the core device are respectively 1.5V and 1V, for example. However, given that the withstand voltage of the I/O device is greater than the withstand voltage of the core device, the prevent invention is not limited to the above exemplary values.
FIG. 1A shows a conventional LDO 10, which adopts a 3.3V I/O device NMOS transistor MN_3P3 as a driving stage. A 3.3V power line AVDD3P3 is used as the main input power line in the LDO 10 to expectantly generate a stable 1.0V voltage at an output power line LDO_OUT. The output power line LDO_OUT may serve as the clock tree power line AVDDTREE to power a clock tree required by an I/O circuit satisfying the double data rate (DDR) specifications. However, the LDO 10 suffers from a severe drawback of being extremely power consuming. In normal operations, in a stable state, because the drain-source voltage (VDS) of the NMOS transistor MN_3P3 is as high as 2V and consumes electric power that is a product of the output current of the LDO 10 and 2V, the NMOS transistor MN_3P3 consumes a substantial amount of electric power.
FIG. 1B shows another conventional LDO 20. The main input power line of the LDO 20 is a 1.5V I/O power line AVDD1P5, and the LDO 20 uses an I/O device NMOS transistor MN_1P5 as a driving stage. The LDO 20 is more power saving than the LDO 10 since VDS of the NMOS transistor MN_1P5 is only 0.5V. However, to achieve a sufficient driving current with such low VDS and further under considerations of silicon area and power supply rejection ratio (PSRR), the realization of the NMOS transistor MN_1P5 is made enormously challenging.